1. Field of the Invention
The invention relates to a method for use in brazing an interconnect pin to a metallization pattern existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate.
2. Description of the Prior Art
A multi-chip integrated circuit package employing the well-known "flip-chip" technique utilizes a multi-layer ceramic substrate (MLC)--constructed of a plurality of laminated ceramic layers. All the individual chips are mounted to the top layer of the MLC substrate. A pre-defined metallization pattern lies on each ceramic layer within the substrate. Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips. Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called "vias". Interconnect pins are bonded to metallic pads situated on the face of the MLC substrate and are thereby connected to appropriate metallization patterns existing within the substrate. These interconnect pins route electrical signals between a multi-chip integrated circuit package and external devices.
One well known technique of mounting an interconnect pin to such a metallic pad involves coating the pad and the pin with a protective metallic layer that serves as a diffusion barrier, and thereafter coating the pad and the head of the pin with an appropriate brazing alloy, and then brazing the pin to the pad. Unfortunately, this technique often produces stress between the pad and the underlying ceramic substrate that can lead to fractures in the ceramic situated directly beneath the pad.
This stress originates from two sources: from the interface between the metallic pad and the MLC substrate, and from the brazed joint itself. Specifically, the MLC substrate is rather brittle and has a thermal coefficient of expansion different from that of the pad. Consequently, due to the thermal expansion mismatch at the interface between the pad and the MLC substrate, the ceramic situated directly beneath the pad is placed in considerable stress.
In addition, the brazed joint imparts considerable tensile stress to the pad which is directed through the pad to the underlying MLC substrate. Although the predominant mechanism causing this phenomenon is not completely known, it appears that several factors are at least partially responsible. First, there is a thermal expansion mis-match between the braze and the pad. Second, during brazing, various elemental constituents of the brazing alloy migrate into the pad and form inter-metallic compounds therein which greatly increase the stress occurring within the pad. Third, the braze often becomes embrittled when it reacts with other materials to which the MLC substrate is exposed during its fabrication.
In any event, the tensile stress resulting from the braze additively combines with the stress resulting from the thermal coefficient mis-match, between the pad and the MLC substrate, to produce the total tensile stress exerted on the substrate. A ceramic layer is quite weak in tension. Furthermore, this total stress is greatest around the edges of the pad. Consequently, at the edges, the total tensile stress exerted onto the MLC substrate often disadvantageously reaches a level sufficiently high to fracture the ceramic situated directly under the pad. This fracturing can cause the interconnect pin and the pad to mechanically separate from the substrate, thereby ruining the integrated circuit package.
The art has taught that this tensile stress can be reduced by two techniques. First, as disclosed in N. Ainsle et al, "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol. 21, No. 8, January 1979, page 3117, and in N. Ainsle et al, "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol. 21, No. 8, January 1979, page 3118, the brazing alloy can be changed to one which imparts a relatively low value of stress to a metallic pad. While this appears to be a theoretically simple and ideal solution, it is often extrememly difficult to implement in practice. First, a multi-chip integrated circuit package contains a pre-determined thermal hierarchy, i.e. certain components of the package--such as solder joints between individual chips and the MLC substrate--must melt before other components. This ensures that a chip can be heated to a temperature which will only weaken the solder joint between it and the MLC substrate and enable the chip to be removed from the substrate without damaging other portions of the package. Consequently, the operating temperatures of the chosen brazing alloy must fall within certain prescribed ranges in this hierarchy. Second, both the pad and the interconnect pin are generally fabricated using an underlying alloy having a multilayered metallic coating. Unfortunately, various elemental constituents (particularly tin) of the brazing alloy will often migrate into one or more of the layers comprising the pin and/or the pad and form inter-metallic compounds which greatly increase the tensile stress occurring therein. To prevent this, an appropriate metallic diffusion barrier is applied over both the pin and the pad before applying the brazing alloy. Although such diffusion barriers exist for many brazing alloys, appropriate barriers do not exist for others. Lastly, different brazing alloys become overly ductile or overly elastic when brazed and are thus unsuitable to bond an interconnect pin to a metallic pad. Hence, choosing a different brazing alloy generally requires that the metallurgy of many, if not all, of the interconnects (i.e. the separate metallurgies comprising the socalled interconnect hierarchy) existing within the MLC substrate be completely re-assessed and possibly re-designed. Thus, once the metallurgy of all the interconnects has been determined which of necessity includes selecting an appropriate brazing alloy, substrate manufacturers are quite reluctant to change this alloy.
Second, each metallic pad can be divided into separate non-overlapping wettable segments each surrounded by a non-wettable area. The brazing alloy would only adhere to the wettable areas. This technique produces a bond consisting of many individual brazed joints in which each joint extends over a very small area. Inasmuch as the cross-sectional area of each joint is very small, each of these joints is quite weak. In addition, as the pad is divided into a greater number of increasingly smaller wettable segments, the effective cross-sectional area occupied by all the brazed joints becomes significantly less than that of the pad. Hence, the electrical resistance of the entire bond between the interconnect pin and the pad correspondingly increases. Furthermore, this technique is very difficult and cumbersome to implement in practice. This technique is described, in connection with a solder bond, in R. W. Noth, "Solder Bond", IBM Technical Disclosure Bulletin, Vol. 17, No. 8, January 1975, page 2214.
Hence, a need exists in the art for a method, suitable for use in brazing an interconnect pin to a metallic pad, which will lower the tensile stress between the pad and an adjacent dielectric (e.g. MLC) substrate, occurring during a brazing operation, while eliminating any need to change the brazing alloy and simultaneously permitting a strong, reliable, minimally resistive brazed joint to form between the interconnect pin and the pad.